| Abstract | The phase-locked loop (PLL) is applied in grid-tied systems to synchronise converter operation with grid voltage, affecting converter stability and performance. Synchronous reference frame PLL (SRF-PLL) is a popular grid synchronisation method due to its simplicity and reliability. Normal SRF-PLL cannot suppress DC offset, causing basic frequency and phase oscillations.When a grid is irregular, its bandwidth should be reduced to ensure acceptable disturbance rejection without sacrificing detection speed. To enhance the phase-angle estimation speed and accuracy, the researchers modified structure by adding the pre/in-loop filter in advanced PLLs.The capacity to deliver improved dynamic response and reduced settling time without compromising system stability or the ability to eliminate disturbances is a major issue for PLLs. Among different control methods, SOGI-FLL (second-order generalised integrator-based frequency locked loop) had the best performance. It tracks grid voltage frequency precisely even when there is harmonics,voltage variations, frequency fluctuations, etc. In the event of a dc offset, the calculated frequency incorporates low frequency oscillations. A modified second-order generalised integrator frequency-locked loop (MSOGI-FLL) is presented in this work to address grid voltage anomalies of all types, including dc offset. Using the Waijung Block-set of MATLAB/Simulink, a Modified SOGI-FLL is realized and evaluated by applying abnormal grid voltage situations using a low-cost DSP-based STM32F407VGT microcontroller. The results demonstrate MSOGI-better FLL's performance in harsh circumstances. |
| Item Type | Journal Article |
| Title | Modified Second Order Generalized Integrator-frequency Locked Loop Grid Synchronization for Single Phase Grid tied System Tuning and Experimentation Assessment |
| Author | Brahmbhatt B. Chandwani H. |
| Publication | International Journal of Engineering |
| Page | 283-290 |
| Date | 2022 |
| Journal Abbr | IJE |
| DOI | 10.5829/IJE.2022.35.02B.03 |
| ISSN | 1728144X, 17359244 |
| Language | English |
| URL | https://www.ije.ir/article_139322.html |
| Library Catalog | DOI.org (Crossref) |
| Tags | Phase-locked Loop, Frequency Lock Loop, STM32F407VG Microcontroller, DC-Signal Cancellation Block |
Programming the ARM(R) Cortex(R)-M4-based STM32F4 Microcontrollers with Simulink(R)
Design and performance of cylindrical-parabolic solar collectors with different control systems
Development of a Home Temperature Control Unit based on a Model Predictive Control Strategy
Experimental Analysis of Modified DC-P&O Technique with Arm Controller for a Stand-Alone 40 W PV System
